In a typical multiprocessor system, several processors share at least one memory which they can access via a system bus. Since each processor has access to the shared memory, it is important to maintain cache coherence to ensure that the processor will access updated data and also to ensure that only one processor will write in a single location of the memory at any given time.
Most multiprocessing architectures, such as the PowerPC architecture, have added operations which permit interprocess synchronization. ("PowerPC" is a trademark of IBM Corporation.) One common requirement of such synchronization is the ability to atomically update one or more locations in system memory. The rapid execution of such atomic operations is considered crucial to the performance of shared memory multiprocessors. The operational primitives used for this purpose in multiprocessor systems, such as the PowerPC.TM., are the Load And Reserve and the Store Conditional instructions. For more background information regarding the PowerPC architecture, refer to the PowerPC Architecture Specification for details of the proper use of these instructions.
In order to maintain cache coherence in the multiprocessor systems, MESI protocol is typically used. MESI represents the four states which tell the processors the status of the memory access request. These states are "modified," "exclusive," "shared," and "invalid." "Modified" implies that the data has been modified by another processor. "Exclusive" implies that the requesting processor can immediately modify the requested data. "Shared" implies that other cache lines in other processors need to be erased prior to the requesting processor being able to modify data. "Invalid" implies that a processor does not have data in the requested cache line.
The use of the MESI state typically ensures that only one processor in the multiprocessor system will gain the right to store data into a cache line at any given time, thus multiple processors will not be able to try to store data in the same location at the same time in the shared memory. As a precaution, the "shared" state is typically the initial state sent to the requesting processor for a read request if the cache line also exists unmodified in another processor's cache. The "shared" state assures that no modification is made until the other processors have had a chance to erase their cache line corresponding to the requested cache line, assuming there is another processor which has a cache line corresponding to the requested cache line.
Some memory access requests require that the requesting processor have a requested cache line in an "exclusive" state. In such a case, having the "shared" state instead of the "exclusive" state requires that the requesting processor send a second request to obtain the "exclusive" state. The second request requires additional time, which translates into a direct loss in performance. Accordingly, what is needed is a system and method for improving the performance of a multiprocessor system by decreasing the wait time required to complete certain requests. In particular, a system and method is needed to improve performance for interprocessor synchronization operations in multiprocessors using the MESI coherence protocol. The present invention addresses such a need.